The present invention relates to a chemical-mechanical polishing process, and particularly to a chemical-mechanical polishing process for planarizing at least one or more of thin films formed on a substrate (wafer). The present invention is suitable for forming multilayers of interconnections in a process of fabricating semiconductor devices, particularly, for planarizing interlayer dielectric films or forming metal plugs at high reliability. More specifically, the present invention is suitable for forming multilayers of interconnection used for memory elements or logic operation elements having highly fine and highly integrated structures.
The interconnection technology is increasingly toward finer geometries and multilayers of interconnections along with high density mounting for devices. The technology for forming multilayers of interconnections comes to play a larger role in a process of fabricating semiconductor integrated circuits. On the other hand, the multilayers of interconnections bring about a new disadvantage.
More specifically, steps of interlayer dielectric films become larger and steeper along with a tendency toward fine geometries and multilayers of interconnections, to thereby cause degradation both in processing accuracy and in reliability of an interconnection formed on the interlayer dielectric films having such steps.
At the present time, it is difficult to improve step coverage of an Al interconnection, and accordingly, the planarity of interlayer dielectric films must be improved for ensuring the processing accuracy and reliability of the above interconnection.
The improvement in planarity of interlayer dielectric films also becomes important because it compensates for a reduction in focal depth with the shortened wavelength of light in lithography. In other words, the improved planarity of interlayer dielectric films makes it possible to keep the resolution already reaching the critical value.
Various technologies for forming dielectric films and planarizing them have been developed. However, when applied to multilayers of interconnections having finer geometries, they present vital disadvantages in terms of shortage of planarity in the case of wide gaps between interconnections and in terms of connection failure between interconnections due to spaces generated in interlayer films in gaps between interconnections.
To improve such disadvantages, a chemical-mechanical polishing process (CMP) for global planarization of interlayer dielectric films has been recently carried out or examined. This process has been originally used for mirror-like polishing for a silicon substrate.
The chemical-mechanical polishing process is expected to positively planarize the entire surface of an interlayer dielectric film. In this process, a polishing cloth is placed on a polishing plate and the polishing plate is rotated while slurry is supplied on the polishing cloth. At the same time, a substrate disposed on a carrier is rotated and pressed on the polishing cloth, to thus polish a dielectric film formed on the surface of the substrate. At this time, KOH or the like is added to the slurry for etching the dielectric film in a basic atmosphere.
In the practical use, cleaning is performed after chemical-mechanical polishing for sufficiently removing the residual slurry and the like, thus completing the planarization.
This process, however, has a disadvantage in processing speed, that is, polishing rate. Specifically, the polishing is as low as about 100 nm/min. This is inconvenient for the future chemical-mechanical process in terms of the increased cost due to poor productivity.
In recent years, one approach using a cerium base slurry, that is, a slurry containing particles of cerium oxide has been proposed. This is expected to obtain a polishing rate being 3 to 4 times that in the case of using a related art silica base slurry. The cerium base slurry, on the other hand, presents a problem in poor planarity of the processed surface and in poor level of metal impurities, and therefore, it actually fails to exhibit the expected result.